A Comprehensive Guide to MOS Tube Selection

In electronic circuit design, the selection of MOS transistors is a crucial step. Choosing MOS transistors correctly not only ensures efficient and stable operation of the circuit, but also effectively controls costs. The following will provide a detailed introduction to the selection method of MOS transistors from multiple aspects.

1、 Classification of Field Effect Transistors

Field effect transistors are divided into two types: junction type (JFET) and metal oxide semiconductor type (MOSFET). JFETs are almost not used in practice, while MOSFETs are widely used and are generally referred to as MOSFETs. There are two main structural forms of MOS transistors: N-channel type and P-channel type. According to the different principles of field effects, it can be divided into two types: depletion type and enhancement type. MOS transistors can be manufactured into four types of products: P-channel enhancement type, P-channel depletion type, N-channel enhancement type, and N-channel depletion type. On the motherboard, enhanced MOS transistors are most commonly used, with NMOS mostly used for signal control, PMOS mostly used for power switches, and depletion type almost not used.

2、 The distinction between N and P channels

Each MOS transistor is provided with three electrodes: Gate gate (represented as "G"), Source source (represented as "S"), and Drain drain (represented as "D"). When wiring, the power input for N-channel is D and the output is S; the power input for P-channel is S and the output is D; and the connection methods for enhancement and depletion are basically the same. The red arrow pointing to the G pole is NMOS, and the arrow pointing away from the G pole is PMOS.

3、 Parasitic diode

Due to the production process, most MOS transistors have a parasitic diode, also known as a body diode. The parasitic diode of NMOS is from the S pole to the D pole, while that of PMOS is from the D pole to the S pole. Parasitic diodes, like ordinary diodes, conduct when connected in the forward direction and turn off when connected in the reverse direction. In some applications, body diodes may also be chosen to reduce the voltage drop between DS, but attention should be paid to the overcurrent capability of the body diodes.

4、 Selection steps

In typical power applications, when a MOS transistor is grounded and the load is connected to the main voltage, the MOS transistor constitutes a low voltage side switch, and an N-channel MOS transistor should be used. When the MOS transistor is connected to the bus and load ground, a high voltage side switch is required, usually using a P-channel MOS transistor. To select devices suitable for the application, it is necessary to determine the voltage required for the driving device and the simplest method to implement in the design.

The higher the rated voltage, the higher the cost of the device. From a cost perspective, it is also necessary to determine the required rated voltage, which is the maximum voltage that the device can withstand. According to practical experience, the rated voltage should be greater than the main line voltage or bus voltage, usually leaving a voltage margin of 1.2 to 1.5 times, in order to provide sufficient protection and prevent MOS transistor failure. Designers must test the voltage variation range throughout the entire operating temperature range. The rated voltage must have sufficient margin to cover this range of variation, ensuring that the circuit will not fail. The rated voltage for different applications also varies. For example, portable devices use 20V MOS transistors, FPGA power supplies use 20-30V MOS transistors, and MOS transistor VDS is 450-600V for 85-220V AC applications.

After determining the current and voltage, the next step is to determine the current of the MOS transistor. It needs to be determined based on the circuit structure, and the rated current of MOS transistor should be the maximum current that the load can withstand in all situations. The determination of current needs to be approached from two aspects: continuous mode and pulse peak. In continuous conduction mode, the MOS transistor is in steady state, and current continuously flows through the device. Pulse spike refers to a large amount of surge (or spike current) flowing through the device. After selecting the rated current, it is also necessary to calculate the conduction loss.

Consider the on resistance MOS transistor as a variable resistor when "conducting", determined by the device's on resistance RDS (ON), and significantly changing with temperature. The higher the voltage VGS applied to the MOS transistor, the smaller the RDS (ON) will be; On the contrary, the RDS (ON) will be higher. For system designers, this requires a trade-off.

5、 Pay attention to the parameters

Choose PMOS or NMOS. NMOS has low on resistance, low heat generation, allows for large current flow, multiple models, and low cost. It is commonly used in topology circuits such as forward, reverse, push-pull, half bridge, and full bridge. PMOS models are few and expensive, commonly used in power switch circuits.

The voltage includes the drain source voltage Vds, gate source voltage Vgs, and gate conduction voltage VGS (th). Limit voltage: Vgs, Vds. Drive voltage: Vgs, the larger the better, and the larger the on resistance Rds (on), the smaller the on resistance. The gate conduction voltage VGS (th) is the turn-on voltage of the MOS transistor.

The continuous leakage current Id should be greater than the peak current. Usually, the larger the size, the smaller the on resistance Rds (on) and the larger the allowed Id. Id is also related to Vgs and Vds. The higher the voltage, the higher the current.

The smaller the parasitic capacitance, the better the switching rate.

The operating temperature of the junction temperature MOS transistor cannot exceed 90% of the junction temperature, otherwise a heat sink must be added.

6、 Special application scenarios

When using a 5V power supply in low-voltage applications, if using a traditional totem pole structure, the actual voltage applied to the gate is only 4.3V due to the voltage drop of about 0.7V caused by the transistor. At this time, choosing a MOS transistor with a nominal gate voltage of 4.5V carries risks. The same problem also occurs when using 3V or other low-voltage power sources.

The input voltage for wide voltage applications is not a fixed value and can vary, resulting in unstable driving voltage provided by the PWM circuit to the MOS transistor. To ensure the safety of MOS transistors at high gate voltages, many MOS transistors are equipped with built-in voltage regulators to forcibly limit the amplitude of the gate voltage. In this case, when the provided driving voltage exceeds the voltage of the voltage regulator, it will cause significant static power consumption. Meanwhile, if the gate voltage is simply reduced using the principle of resistive voltage division, the MOS transistor will work well when the input voltage is high, but the gate voltage will be insufficient when the input voltage decreases, causing incomplete conduction and increasing power consumption.

Dual voltage is applied in some control circuits, where the logic part uses typical 5V or 3.3V digital voltages, while the power part uses 12V or even higher voltages, and the two voltages are connected in a common ground manner. This requires the use of a circuit that allows the low-voltage side to effectively control the MOS transistor on the high-voltage side.